A Rail-to-rail High Speed Class-ab Cmos Buffer with Low Power and Enhanced Slew Rate

A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at 45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuit is performed with extremely low leakage current as well as high current driving capability for the large input voltages. The proposed paper is achieved very high speed with very low propagation delay range i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by 24% (in ns) at 3V square wave input. The measured quiescent current is 41μA.